Many semiconductor components, for example DRAM (Dynamic Random Access Memory) semiconductor memories require, for their operation, internally regulated voltages that are derived from an external supply voltage. The internal voltages are fed into an internal voltage network of the semiconductor component. Voltage regulating circuits are used to compensate for voltage fluctuations in the internal voltage network.
FIG. 7 shows a so-called push-pull generator 30 for generating an output voltage Vout that is fed into an internal voltage network of an integrated circuit. The push-pull generator 30 has a first controllable resistor 31 and a second controllable resistor 32. The two controllable resistors are embodied as transistors in the exemplary embodiment of FIG. 7. The transistor 31 is embodied as a p-channel transistor and connects an input terminal E30a for applying a supply voltage VDD to an output terminal A30 for generating the output voltage Vout. The transistor 32 is embodied as an n-channel transistor and connects an input terminal E30b for applying a reference voltage VSS to the output terminal A30 for generating the output voltage Vout. The resistances of the controllable paths of the transistors 31 and 32 can be controlled by control signals Pout and Nout at their control terminals S31 and S32.
For generating the control signal Pout, the control terminal S31 of the transistor 31 is driven by a comparator circuit 10. The comparator circuit 10 is embodied as a differential amplifier connected between a terminal V10a for application of a supply voltage VDD and a terminal V10b for application of a reference voltage VSS. The differential amplifier 10 has an input transistor 11 with an input terminal E10a for application of a reference voltage Vref_P and an input transistor 12 with an input terminal E20a, from which the output voltage Vout of an internal voltage network of the integrated circuit is fed back into the comparator circuit 10. The input transistors of the differential amplifier 10 are embodied as n-channel transistors. The two input transistors 11 and 12 are connected via an active load 13, which comprises the two p-channel transistors 13a and 13b connected as a current mirror, to the supply terminal V10b for application of the reference voltage VSS. A controlled current source 14 is connected into a common branch of the two input transistors 11 and 12 that connects the input transistors to the terminal V10a for application of the supply voltage VDD. In the exemplary embodiment of FIG. 7, the controlled current source is designed as an n-channel transistor, it being possible to set the current in the common branch by applying an operating point signal BS1 to a control terminal S14.
The control terminal S32 of the n-channel transistor 32 is driven with the control signal Nout by a second comparator circuit 20. The comparator circuit 20 is designed as a complementary differential amplifier in comparison with the differential amplifier 10. The differential amplifier 20 has a first input transistor 21, which is driven by a reference voltage Vref_N at an input terminal E20a, and a second input transistor 22 with an input terminal E20b, to which the output voltage Vout of the internal voltage network is fed back. The differential amplifier circuit 20 is connected between a terminal V20a for application of the supply voltage VDD and a terminal V20b for application of the reference voltage VSS. The p-channel input transistors 21 and 22 are connected via an active load 23, which has the two n-channel transistors 23a and 23b connected as a current mirror, to the terminal V20b for application of the reference voltage VSS. A common branch of the input transistors 21 and 22 is connected via a controlled current source 24 to the terminal V20a for application of the supply voltage VDD. The controlled current source is embodied as a p-channel transistor. The current supplied by it can be set by means of an operating point signal BS2 at a control terminal S24 of the p-channel transistor 24.
FIG. 8 illustrates the functioning of the regulable push-pull generator of FIG. 7. The illustration shows the voltage levels of the first and second control signals Pout and Nout generated by the comparator circuits 10 and 20 against a current I fed into the internal voltage network, and also against the output voltage Vout of the internal voltage network the voltage Vout of the internal voltage network is intended to be held at a constant voltage level Vdesired by the circuit arrangement illustrated in FIG. 7. In the case of an overvoltage, if the voltage Vout of the internal voltage network is greater than the desired voltage Vdesired, the p-channel transistor 31 is driven by a high level in the vicinity of the supply voltage VDD. The controllable path of the p-channel transistor 31 is thereby controlled in high-resistance fashion (or a high-resistance state). At the same time the control terminal S32 of the n-channel transistor 32 is driven by a level of the control signal Nout that lies between the supply voltage VDD and the reference voltage VSS, for example a ground potential. The controllable path of the n-channel transistor 32 is thereby controlled in low-resistance fashion (or a low-resistance state), so that the output terminal A30 of the voltage generator circuit 30 connected to the internal voltage network is connected to the reference voltage VSS in low-resistance fashion. A current I<0 thus flows, which current flows away from the internal voltage network to the input terminal E30b for application of the reference voltage VSS.
If the voltage Vout of the internal network is less than the desired voltage Vdesired, that is to say a case of undervoltage is present, the n-channel transistor 31 is driven, by the comparator circuit 10, with a level of the control signal Pout that controls the controllable path of the p-channel transistor 31 in low-resistance fashion. The internal voltage network is thus connected to the supply voltage VDD in low-resistance fashion via the output terminal A30 of the voltage generator circuit 30 and the p-channel transistor 31. The comparator circuit 20 drives the control terminal S32 of the n-channel transistor 32 with a low level of the control signal Nout that is close to the reference voltage VSS. The controllable path of the n-channel transistor 32 is thus controlled in high-resistance fashion.
The controllable paths of the transistors 31 and 32 are controlled in high-resistance fashion in a small range T2 around the level of the desired voltage Vdesired. This is intended to prevent a high shunt current from flowing from the input terminal E30a of the voltage generator circuit 30 for application of the supply voltage VDD to the input terminal E30b for application of the reference voltage VSS via the transistors 31 and 32. However, a shift in the operating points of the two complementary differential amplifiers may occur on account of external influences, e.g. as a result of process or temperature fluctuations. As a result, the curve of the control signal Pout illustrated in FIG. 8 is shifted toward the left and the curve of the control signal Nout is shifted toward the right. The so-called dead zone T2, in which both transistors are controlled in high-resistance fashion, gradually disappears. As a result, both transistors 31 and 32 are controlled in low-resistance fashion in a range around the desired voltage Vdesired. The consequence is a large shunt current between the input terminal E30a and the input terminal E30b of the voltage generator circuit. The current consumption of the voltage generator circuit thus rises considerably.
A simple measure for preventing the shunt current consists in enlarging the dead zone. However, this leads to an increased tolerance with respect to deviations from the desired voltage level Vdesired of the internal voltage network, since the two transistors 31 and 32 of the push-pull generator 30 are only regulated in the event of a larger deviation from the desired value Vdesired.